1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cell arrays, e.g., in the form of DRAMs in a memory chip, and a method of testing the semiconductor memory device.
2. Description of the Related Art
In recent years, as highly integral circuit technologies have been introduced in the semiconductor industries, the cost per bit of memories is significantly decreased. However, the increasing demand for memory device now requires an advanced technology for more reduction of the cost. It is however known that as advanced memories for mass storage are developed, their testing process now claims a considerable length of time. This may inhibit the cost reduction, hence hardly permitting more decrease in the cost per bit of memories.
For overcoming the foregoing drawback, some methods are proposed of reducing the time required for testing a semiconductor memory device of bank switching type where a plurality of memory array banks are mounted in a memory chip, and switched from one to another for storage operation. As one of such methods, a multi-bit test is well known, which is a sort of multi-bit parallel test method, for writing one identical data onto a number of bits at once and examining the data read from their corresponding bits for matching or mismatching. In a normal operation mode of the semiconductor memory device, one-bit data received from a DQ pad is written onto and read from each memory cell. In a multi-bit test mode of the semiconductor memory device, one-bit data received from the DQ pad are written onto and read from a plurality of memory cells at once before returned back to the DQ pad.
The write/read operation in both the normal mode and the multi-bit test mode of the conventional semiconductor memory device of a bank switching type will now be explained referring to FIGS. 10 to 13. FIG. 10 is a block diagram schematically showing the conventional semiconductor memory device of a bank switching type. The semiconductor memory device denoted by 80 includes four memory array banks 81A to 81D provided in a memory chip. Each of the memory array banks 81A to 81D has a plurality of memory arrays (only two shown in FIG. 10). Each memory array is connected by a data bus 82 to a DQ input/output circuit 84.
An information data EXTDQ received from the outside is passed through the DQ input/output circuit 84, sent to the memory array in the memory array bank addressed by an address data EXTA received together with the information data EXTDQ via the data bus 82, and written onto a corresponding memory cell. The information data in the memory cell is read out in response to the input of reading command for the memory cell, sent to the DQ input/output circuit 84 via the data bus 82, and output to the outside.
FIG. 11 illustrates a detail of the memory array bank 81B. The memory array banks 81A, 81C, and 81D are identical in the structure to the memory array bank 81B. The memory array bank 81B includes four memory arrays 85a to 85d, four sense amplifiers 86a to 86d connected to the corresponding memory arrays 85a to 85d, and four I/O circuits 91a to 91d, as the transmission paths of information data. Also, the memory array bank 81B has a column decoder 87, a column address buffer 88 connected to the column decoder 87, a row decoder 89, and a row address buffer 90 connected to the row decoder 89, as the transmission path of address data. The sense amplifiers 86a to 86d are connected by sub data buses 92a to 92d to the I/O circuits 91a to 91d respectively.
In the memory array bank 81B, on the occasion of data writing in a normal mode, a one-bit information data received at the input (not shown) of the DQ input/output circuit 84 is sent via the data bus 82 and written onto a memory cell at the intersection between a row address and a column address in the memory array determined by the address data. For example, in the memory array 85a, the information data received via the DQ input/output circuit 84 is written onto the memory cell (denoted by “A”) assigned at the intersection between a word-line (denoted by “WL”) selected by the row decoder 89 and a column-select-line (denoted by “CSL”) selected by the column decoder 87.
On the occasion of data writing in the multi-bit test mode, the information data received via the DQ input/output circuit 84 is written simultaneously onto four memory cells (denoted by “A” to “D”) assigned at the intersection between a word-line and a column-select-line, for same row and column address, in memory arrays 85a to 85d. 
On the occasion of data reading in the normal mode, the data are read out from the memory cells assigned at the intersection between a word-line selected by the row decoder 89 and a column-select-line selected by the column decoder 87 in memory arrays 85a to 85d. The data are transmitted via the sense amplifiers 86a to 86d, the sub data buses 92a to 92d, the I/O circuits 91a to 91d, the data bus 82, and the DQ input/output circuit 84 and output to the outside.
On the occasion of data reading in the multi-bit test mode, the data are read out from the memory cells A, B, C, and D shown in FIG. 11 by energizing the four column-select-lines at once similar to the writing operation, passed via the sense amplifiers 86a to 86d, the sub data buses 92a to 92d, and I/O circuits 91a to 91d, and loaded to the data bus 82.
As the data bus 82 basically includes a pair of lines DB (data bus) and ZDB, its paired lines are provided on a layout pattern depending on the type of the memory device. For example, when the memory device is of x16 type, the data bus 82 has sixteen pairs of lines. When x8 type, the data bus 82 has eight pairs of lines. While the data bus 82 is patterned in such manner, each of the I/O circuits 91 to 91d includes a data bus drive circuit 93 (referred to as a DB drive circuit hereinafter) for DB-ZDB lines as best shown in FIG. 12. When receiving a H level signal from the memory cell, the DB drive circuit 93 provides an “H” drive on the DB line and an “Hi-Z” (high impedance) drive on the ZDB line. On the other hand, when receiving an L level signal from the memory cell, the DB drive circuit 93 provides an “Hi-Z” drive on the DB line and an “H” drive on the ZDB line.
The data bus 82 performs a wired-or action on each data from the four memory cells and its wired-or signal is transmitted to the DQ input/output circuit 84. On the occasion of data writing, the same data is simultaneously written on four memory cells. Accordingly, when non of the four memory cells is defective, the four data read out from their respective memory cells are identical thus providing the H level on either the DB or ZDB line. When the read-out data is an H level signal, the DB line draws “H” and the ZDB line draws “L(Hi-Z)”. When the read-out data is an L level signal, the DB line draws “L(Hi-Z)” and the ZDB line draws “H”.
If any of the four memory cells is defective, the read-out data include both H and L levels hence causing both the lines DB and ZDB to draw “H”. When any of the four memory cells is defective and the read-out data include both H and L levels, the “H” level on both the lines DB and ZDB is received by the DQ input/output circuit 84.
Upon receiving a result from the four memory cell data, the DQ input/output circuit 84 performs a pass/fail operation. More specifically as shown in FIG. 13, the DQ input/output circuit 84 has a logic that it judges “passed” when the DB line and the ZDB line draw “H” and “L”, or “L” and “H” respectively and “failed” when both the DB and ZDB lines draw “H”. FIGS. 14 and 15 are timing charts of the signals when the multi-bit test mode provides “passed” and “failed” respectively. The symbols (e.g. EXTCLK, EXTA, and EXTDQ) shown in FIGS. 14 and 15 represent the signals announced in the output side of the DQ input/output circuit 84 shown in FIG. 13.
As described above, the multi-bit test allows the multiple memory cells in different memory arrays to be tested at once thus contributing to the reduction of the time required for testing the semiconductor memory device 80.
However, the paired lines DB and ZDB of the data bus 82 are located adjacent to each other in a layout pattern. As the memory cells are improved in the down-sizing and the integral level, the generation of a parasitic capacitance C between the paired lines may hardly be negligible (See FIG. 16). When any paired lines adjacent to each other of lines in the data bus 82 are energized in the multi-bit test mode, their induced parasitic capacitance C may produce a coupling noise which elevates the level of the data bus 82 on “L(Hi-Z)” side. As a result, its level is detected as “H” level and may interrupt the pass/fail operation of the DQ input/output circuit 84 thus leading to a fault decision.